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| AN156 Application Note USING THE CS7620/22 WITH CCDS INTRODUCTION This application gives an overview of how to use the CS7620/22 with different CCDs. Each short example explains the different modes and signals involved. cal driver/CCD. It only requires external clock, EXPOSE and POWER DOWN signals. When PWR_DN is high, all of the CS7620 powers down except for the DAC outputs (which may be powered down through register controls). The EXPOSE signal should go high at the beginning of exposure and low at the beginning of read out. The LINE_ENA and CLAMP are not used in Master Mode and should be tied low. The use of two vertical drivers is suggested in the Sony ICX205AK datasheet. Note that the two internal DACs can be used for any bias used for the CCD. Example #1 : CS7620 in Master Mode: To select this mode, the user must set the BYPASS_PLL pin LOW and select the proper internal timing mode in the timing mode register (See CS7620 Register Configuration). The CS7620 will provide vertical and horizontal outputs to the verti- CCD_out Bypass PLL Data 12:0 Clock ICX205AK CCD H1, H2 CS7620 Along Front End Expose To/From DSP or Backend Power Down CXD1267AN V-Drive + CCD Bias V[4:1] Figure 1. Master Mode P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved) JUL `99 AN156REV1 1 AN156 Example #2 : CS7620 in Slave Mode: In this example, the Sony Timing Generator/Vertical Driver is used to generate all the timing information. In this configuration, the CS7620 is in Slave Mode, therefore it requires all the timing information from an external source. The user must set the BYPASS_PLL pin HIGH and provide the following signals: EXPOSE, POWER DOWN, CLAMP, CLK_FT and CLK_DT. The EXPOSE signal is redefined as a non-readout signal. This is used so that the back end processor can account for the chip latency. The POWER DOWN pin may be Vcc Data 12:0 use to save power. CLAMP should be high when over the DARK reference pixels. CLK_FT and CLK_DT are respectively used to sample the Feedthrough level and the pixel (data) level (See Figure 2). CK_FT and CK_DT: The XTAL_IN and LINE_ENA pins are redefined as the CK_FT and CK_DT signals, which sample the feedthrough and data levels, respectively. The timing for CK_FT and CK_DT is shown in Figure 3. Note that these clocks are non-overlapping. ICX205AK CCD Bypass PLL CCD_out Clock CS7620 Along Front End Expose Power Down Clamp To/From DSP or Backend V[4:1], H[2:1}, RG CXD12460OR V-Drive/T.G. CLK_FT, CLK_DT Figure 2. Slave Mode CCD Input Signal CK_FT CK_DT Figure 3. Clock Timing 2 AN156REV1 AN156 Example #3 : CS7620 in Partial Master Mode: To select this mode, the user must set the BYPASS_PLL pin LOW and the select external timing mode in the timing mode register. The CS7620 is the master of the pixel rate timing, but the line and frame timing is controlled elsewhere. In this mode, the user must control four signals: PWR_DN, EXPOSE, LINE_ENA, and CLAMP. The master PWR_DN signal may be used to conserve power during non-readout time. The EXBypass PLL CCD_out POSE pin is redefined as a non-readout time signal. This is used so that the back end processor can account for the chip latency (See Figure 4). The LINE_ENA signal should be high during the vertical shift and load times, and CLAMP should be high when over the dark reference pixels. The suggested timing for these signals is shown in Figure 5. Note that the chip should be powered up at least 500 us before the beginning of readout. The CLAMP signal may also be high during the dark pixel lines at the beginning of the frame. Data 12:0 Clock ICX205AK CCD H1, H2 CS7620 Along Front End Expose Power Down Clamp To/From DSP or Backend V[4:1] LIne_Ena CXD2460OR V-Drive/T.G. Figure 4. Partial Master Mode Clamp Signal Line_ena Signal V Shift & Load Extended Pixels Dark Pixels Active Pixels Active Pixels V Shift & Load TLINE Figure 5. Clamp and Line Enable TLINE+1 NOTE: In partial master mode, we have full programmability over the four horizontal signals (H1-H4) and the RG signal. This means that the rise and fall time of each signal can be individually programmed. Each adjustment made on the rise and fall time has a step of one-eighth of the pixel clock. Through reg. 2C, H1-H4 and RG delay can be fine tuned to ensure optimum sampling time with a resolution of 1.5 ns. AN156REV1 3 AN156 CS7620 Register Configuration: To use the CS7620 with the Sony imager a handful of registers need to be modified. Set tim_modes in Operation Control 1 register (address 06h) for Sony imager: Example #4 : CS7622: In this example, the Sony Timing Generator/Vertical Driver is used to generate all the timing information. The CS7622 is ALWAYS Slave to the timing generator, therefore it requires all the timing information from an external source (See Figure 6). The presence of black pixels in the CCD output is indicated by the CLAMP pulse, which must be fed to the CS7622. The input clocks CLK_FT and CLK_DT are used to set up the sampling times and also to generate the digital clock. These clocks need to be running when processing pixels from the CCD, accessing the registers or performing calibration. The timing of these clocks is important to ensure optimum settling times and sampling the correct value. CLK_FT and CLK_DT need to be non-overlapping pulses made as wide as possible to give long settling times. The falling edge of CK_FT should be close to the end of feedthrough while the falling edge of CK_DT should be close to the end of the data section of the CCD signal. See figure 7, connection diagram, for more details on how to interface the CS7622. Master Mode tim_modes [2:0] set to 011 for low resolution timing tim_modes [2:0] set to 100 for high resolution timing H clocks programmed through reg. 29h-2Ch Slave Mode tim_modes [2:0] set to 111 - bypass pll high Partial Slave Mode tim_modes [2:0] set to 111 - bypass pll low, H clocks programmed through reg. 29h-2Ch. The amount of exposure measured in line lengths can be controlled through reg. 23h-24h. The n_extra[10:0] allows for increased exposure time while in low resolution mode. The H clocks must also be programmed for the sony CCD (Reg. 29h2Ch). Data 12:0 Clock ICX205AK CCD CCD_out CS7622 Along Front End To/From DSP or Backend Clamp V[4:1], H[2:1}, RG CXD12460OR V-Drive/T.G. CLK_FT, CLK_DT Figure 6. CS7622 (Always Slave) 4 AN156REV1 AN156 ICX205 RG H1 H2 V1 V2A V2B V3 SUB CXD2460R AIN CS7622 DOUT[12:0] CLKO XSHP XSHD XCPOB CK_FT CK_DT CLAMP BG. RES 10 K 1% SDAT1 SDAT0 SCLK Control Port Figure 7. Connection Diagram Non-Overlap clock generator circuit: This circuit will allow you to generate a non-overlap clock. CK_DT Input Clock CK_FT Figure 8. Non-Overlap Clock Generator * Refer to CS7622 Datasheet for timing information. AN156REV1 SEN 5 CKO CKI OSC0 OSCI 3 4 5 AVD0 AVD1 AVD2 Vpp0 VDD1 MMBD914LT1 28 test1 test2 Vss4 20 36 4.7uF 0.1UF 4.7uF CXD2460R U?A 1 2 + + + + 6 15V 15V U? 3.3V 15V 1 8 14 16 6 26 C? C? U? 0.01uF + C? 22uF R? 51R D? 3 4 2 1 Vo2B Vo3 Vo2A Vo1 Vout GND2 Ho1 Ho2 VL 17 VDD 11 + C? 0.1UF + C? 0.1UF + C? 0.1UF C? + C? 0.1UF + C? + 0.1UF C? 4.7uF 0.1uF 15 17 18 19 21 22 24 47 29 30 31 48 32 33 34 35 37 38 XCPDM XSHP XSHD XRS PBLK XCPOB RST DSGAT SEN SSK SSI PS id exp HRO FRO HRI FRI RG H1 H2 V1 V2A V2B V3 SUB ADCLK 9 + 12 13 40 42 44 41 45 0.1uF 19 20 10 9 100R -8V R? Q? BFR92A C? 11 U? 3.3V 3.3V AIN VDDA 13 C? 18 CSUB oRG NC1 NC2 NC3 NC4 NC5 oSUB 13 15 C? 0.1uF R? 1K0 0.1uF 8 6 7 5 SENB SDATO SDATI SCLK VDDD 28 0.01uF C? + 0.47uF 16 14 5 6 8 23 2MCK MCK VL VH 27 25 46 15V -8V GND1 GND3 7 12 DO12 DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 4 3 2 1 32 31 30 27 26 25 24 23 22 21 C? 0.01uF C? 0.1uF 16 9 DIAG0 TEST ICX205AK C? 43 17 0.1uF VM Vss0 Vss1 Vss2 Vss3 39 2 10 11 C? R? 1M C? 2200pF C? 0.1uF + 3.3uF 18 19 20 RESET CLAMP CK_FT C? C? C? C? R? 100K 7 CLKO CK_DT REF_CP GNDA REF_CN GNDD BG_RES 0.1UF C? + 15 14 10 12 29 1uF 74HC04 U?A 1 2 R? 10K, 1% CS7622 74HC04 U?A 1 2 74HC04 select blue box to zoom into this schematic AN156REV1 AN156 * Notes * |
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